A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70nm technology

For the first time, a new DRAM cell layout as the key enabler for future DRAM shrink generations based on deep trench (DT) technologies with a planar array device is presented. The work describes the full integration scheme in 70nm technology and the major technology features of the 'checkerboard (CKB)' layout. The new layout is beneficial for lithography and high aspect ratio etch processes. In addition, the high degree of symmetry enables easily the integration of a self aligned trench bottling process on a [100] rotated substrate with an outstanding utilization of area for the capacitor. Further capacitance enhancement up to 50% is achieved for the first time in a trench process by introduction of hemispherical silicon grains (HSG) with high k dielectric material (Al/sub 2/O/sub 3/). Additionally, a new self aligned trench-cell connection (single sided buried strap) technique with a novel isolation trench (IT) pre fill process will be presented in the paper.

With shrinking ground rule DRAM technology faces huge challenges.

While shrinking the DRAM ceJl device the substrate doping level has to be increased to overcome short channel effects. On the other hand, however, the data retention time is strongly impacted by the electric field across the device junction connected to the DRAM storage capacitor. The breakdown of data retention time with increasing electric field is widely reported and basically originates from increasing junction leakage with doping concentration. Different solutions have been proposed like vertical access transistors in deep trench technology or recessed devices in stack capacitor technology. The basic idea behind these concepts is to increase the array transistor channel length by extending it into the silicon surface and hence enabling lower doping concentrations at the expense, however, of the device drive current.

This paper reports about a planar DRAM cell device within a novel “checkerboard” cell layout. The scalability of the planar array device is based on a highly asymmetnc, inhomogeneous doping profile along the channel. With this concept we are able to extend the planar DRAM cell device to channel lengths as low as 65nm and to maintain a decisive advantage with respect to device drive current.

Another key for maintaining the DRAM data retention time is to compensate the loss of storage capacitance caused by rapid decrease of the feature size. Big efforts for surface enhancement and node dielectric materials have been reported for stack capacitor technique. In deep trench technology very large aspect ratios (width vs. depth of trench) of more than 70:1 are achieved. A comparison of different enhancement techniques used in our deep trench technology generations is summarized in. For the first time, we introduced a high k dielectric material (Al₂O₃) in the 70nm technology reported in this paper.

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A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70nm technology

For the first time, a new DRAM cell layout as the key enabler for future DRAM shrink generations based on deep trench (DT) technologies with a planar array device is presented. The work describes the full integration scheme in 70nm technology and the major technology features of the 'checkerboard (CKB)' layout. The new layout is beneficial for lithography and high aspect ratio etch processes. In addition, the high degree of symmetry enables easily the integration of a self aligned trench bottling process on a [100] rotated substrate with an outstanding utilization of area for the capacitor. Further capacitance enhancement up to 50% is achieved for the first time in a trench process by introduction of hemispherical silicon grains (HSG) with high k dielectric material (Al/sub 2/O/sub 3/). Additionally, a new self aligned trench-cell connection (single sided buried strap) technique with a novel isolation trench (IT) pre fill process will be presented in the paper.